1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a recessed gate electrode and a method of fabricating the same.
2. Description of Related Art
As the integration density of a semiconductor memory device, such as a DRAM device, increases, the planar area occupied by each MOS transistor of the device necessarily decreases. As a result, the channel length of the MOS transistor is reduced, thus causing a short channel effect. In particular, when the short channel effect is generated in an access MOS transistor that is used for a memory cell of the DRAM device, the threshold voltage of the DRAM cell decreases but the leakage current thereof increases, so that the refresh characteristics of the DRAM device may be degraded. Accordingly, a MOS transistor having a recessed gate electrode has been introduced as a MOS transistor that operates to suppress the short channel effect by increasing the gate channel length even in cases where the DRAM device is highly integrated.
A MOS transistor having the recessed gate electrode is fabricated by forming a channel trench in a semiconductor substrate, forming a gate that fills the channel trench, and forming a source and a drain in the silicon substrate on both sides of the gate. During the formation of the gate, a void may be formed in the gate material layer used to fill in the channel trench. When the gate material layer is a lightly doped polysilicon layer, the void can migrate and come into contact with an inner wall of the channel trench during a subsequent annealing process, so that the threshold voltage of the transistor can be caused to drastically increase or the current path of a channel may be entirely cut off.
Meanwhile, a CMOS semiconductor device is a semiconductor device that adopts a CMOS transistor circuit including an NMOS transistor and a PMOS transistor. The CMOS transistor circuit generally consumes less power than an NMOS transistor circuit or a bipolar transistor circuit. A method of fabricating a dual gate electrode to convert all the channel characteristics of the CMOS transistor into surface channel characteristics is proposed in Korean Laid-open Publication No. 2001-0045183. According to Korean Laid-open Publication No. 2001-0045183, a p-well and an n-well are formed adjacent to each other in a substrate in which an isolation layer is to be formed. A gate insulating layer is deposited on the entire surface of the substrate, and an amorphous silicon layer is deposited on the gate insulating layer. N-type impurities are selectively implanted only into the amorphous silicon layer formed on the p-well, while p-type impurities are selectively implanted only into the amorphous silicon layer formed on the n-well. The amorphous silicon layer in which the n- and p-type impurities are implanted is patterned, thereby forming a dual gate electrode. According to the above-described technique, since all the channel characteristics of the NMOS transistor and the PMOS transistor are converted into the surface channel characteristics, the characteristics of both the NMOS transistor and the PMOS transistor can be improved. However, when a cell transistor disposed in a cell region has a recessed gate electrode, n-type impurities cannot be sufficiently implanted into the recessed gate material layer, and thus the characteristics of the cell transistor can be deteriorated and the void is subject to migration, as described above.
In order to enhance the characteristics of the cell transistor having the recessed gate electrode, a method of depositing a polysilicon layer doped with n-type impurities and selectively implanting p-type impurities into a portion of the polysilicon layer corresponding to a PMOS transistor region has been disclosed. However, when the polysilicon layer which is heavily doped with the n-type impurities is deposited in order to enhance the characteristics of the cell transistor and the NMOS transistor, the p-type impurities implanted into the PMOS transistor region cannot counteract the heavily doped n-type impurities. On the other hand, when a polysilicon layer which is lightly doped with n-type impurities is deposited to solve the above-described problem, a poly-depletion effect can occur in an NMOS transistor region. The poly-depletion effect can lead to an increase in the effective thickness of a gate insulating layer, thus causing a variation of the threshold voltage of the transistor. Also, a void may be formed in the recessed gate electrode (i.e., a cell gate electrode) and migrate in a subsequent annealing process as described above.